The present invention relates to disk storage devices for computer systems and, more particularly, to a method and system for providing a fast and efficient comparison of cyclic redundancy check (CRC)/checksum values of two mirrored disks in a RAID level 1 system.
Dramatic increases in computer processing power and speed, and in the speed and capacity of primary memory devices, have been realized in recent years. Unfortunately, in contrast to processing and main memory technology advances, the rate of improvement in performance of secondary memory storage devices, primarily magnetic disks, has been modest. The benefits from the substantial gains and performance in speed which continue to be realized for CPUs and main memory devices will not be fully realized if not matched by similar performance increases in secondary storage devices. For example, as the mismatch in performance of CPU and disk memory increases, disk I/O operations consume a greater proportion of the CPU operating time.
Disk arrays have been proposed as a means to improve the performance of secondary storage devices, eliminating the expensive mismatch between CPU and secondary storage performance. A disk array, comprising a multiplicity of small, inexpensive disk drives connected in parallel, appears as a single, large disk to the host system. In many applications disk arrays offer improvement in performance, reliability, power consumption and scalability over a single large magnetic disk.
Current disk array design alternatives are described in an article titled xe2x80x9cA Case for Redundant Arrays of Inexpensive Disks (RAID)xe2x80x9d by David A. Patterson, Garth Gibson and Randy H. Katz; University of California Report No. UCB/CSD 87/391, December 1987. This article describes five disk array arrangements, referred to as RAID levels. The simplest array system, a RAID level 1 system, comprises one or more disks for storing data and an equal number of additional xe2x80x9cmirroredxe2x80x9d disks for storing copies of the information written to the data disks.
Mirrored disk arrangements are typically used in PC server applications where mission critical data is involved. A mirrored disk arrangement typically includes a primary disk and a secondary disk which holds an exact copy of the contents of the primary disk and is used in case of a failure of the primary disk. It is necessary in this type of disk configuration to guarantee that the contents of the primary and secondary disks are identical.
Prior art RAID 1 implementations used a serialized approach to accessing the contents of these mirrored disks. Each disk""s contents were accessed separately in order to verify the contents of each. With the advent of new controller technology along with the adoption of the EIDE standard, more parallelism in disk access is possible. This enables a hardware oriented approach to verify the contents of the primary and secondary disks and leads to noticeable system improvement in latency and throughput. New controller architectures, such as the SYM89C621 by Symbios Logic, allow concurrent operation of the primary and secondary IDE channels. With these enabling features, more verification is possible in the same amount of time as previous RAID 1 controllers which also leads to better system integrity.
The SYM89C621 is a dual channel bus mastering PCI enhanced IDE (EIDE) controller capable of supporting the fastest standard EIDE transfers, with flexibility that allows for support of future EIDE modes up to and exceeding 20 MB/s. The SYM89C621 is designed for use in PC, host board adaptor, and portable applications providing special features to meet the needs of each of these applications.
The SYM89C621 supports two independent EIDE channels with a separate EIDE data path for each channel. Other IDE controllers multiplex the IDE channels over one shared IDE databus. If more than 2 IDE devices are used without external logic this may cause signal integrity problems. In contrast to this type of design, the SYM89C621 provides complete support for two channels, without any external logic. This provides up to two times higher performance than shared channel devices. Shared data path designs cannot match the SYM89C621 for concurrent data transfer performance nor can they provide the same high quality signal reliability.
Although controllers such as the SYM89C621 have emerged to provide parallel access to two independent EIDE channels, there is no corresponding cyclic redundancy check (CRC), particularly for a RAID 1 system, for testing the data integrity of two mirrored disks, which takes advantage of this new parallel access technology. Thus, there is a need for a system or circuit for performing data integrity checks between two mirrored disks which takes advantage of the parallelism in disk access which is currently possible. Such a system, or circuit, will lead to greater reliability and throughput and faster data accesses by a computer system.
Typically, the term xe2x80x9cCRCxe2x80x9d means an operation in which a dataword, or other segment of data, is inserted into a polynomial function and then truncated in order to detect single or multi-bit errors. The term xe2x80x9cchecksumxe2x80x9d typically refers to the operation of cumulatively adding successive data segments, or datawords, and truncating the result in order to detect errors. However, as used herein, the terms xe2x80x9ccyclic redundancy check,xe2x80x9d xe2x80x9cchecksum,xe2x80x9d xe2x80x9cCRCxe2x80x9d, xe2x80x9cCRC calculation,xe2x80x9d xe2x80x9cchecksum calculation,xe2x80x9d and conjugations thereof, are used synonymously and interchangeably and refer to any algorithm, or mathematical operation, for performing data integrity checks which are well-known in the industry.
The present invention addresses the above and other needs by providing a hardware implemented compare circuit which simultaneously and concurrently receives data blocks from each of the mirrored disks in a dual channel IDE controller architecture.
As used herein, the term xe2x80x9csimultaneously,xe2x80x9d or any conjugation thereof, is synonymous with the term xe2x80x9cconcurrently,xe2x80x9d and means that two processes or steps may occur at the same time as the other. It does not necessarily imply that the two or more processes, or steps, are dependent upon the occurrence of the other. In other words, two processes are said to be concurrently occurring if they have overlapping periods of time in which they are taking place. It is not necessary that the start and the end of one process occur at the same time as that of the other. In order to convey temporal dependence between two or more processes, or steps, the term xe2x80x9csynchronization,xe2x80x9d or any conjugate thereof, is used herein, e.g., xe2x80x9cstep 1 is synchronized with step 2.xe2x80x9d
In one embodiment of the invention, a method of checking data integrity in a computer system, includes: transmitting primary data from a primary device to a primary CRC circuit; transmitting secondary data from a secondary device to a secondary CRC circuit, wherein the primary data and the secondary data are transmitted to their respective CRC circuits concurrently; generating a primary CRC value; generating a secondary CRC value, wherein the primary and secondary CRC values are generated concurrently; and comparing the primary CRC value with the secondary CRC value in order to generate a compare value.
In another embodiment, a method of checking the integrity of data used in a computer system, includes: transmitting primary datawords on a primary channel to a primary CRC circuit; transmitting secondary datawords on a secondary channel to a secondary CRC circuit wherein each primary dataword is transmitted concurrently with a corresponding secondary dataword; generating a new primary CRC value for each primary dataword; generating a secondary CRC value for each secondary dataword; comparing each primary CRC value with a corresponding secondary CRC value; and generating a compare value of xe2x80x9ctruexe2x80x9d if each primary CRC value is identical to the corresponding secondary CRC value, otherwise, generating a compare value of xe2x80x9cfalse.xe2x80x9dIn a further embodiment, the method as described above further includes: synchronizing the transmission of primary datawords to a primary CRC circuit with a feedback of primary CRC values to the primary CRC circuit; and synchronizing the transmission of secondary datawords to a secondary CRC circuit with a feedback of secondary CRC values to the secondary CRC circuit.
In yet another embodiment, the method as described above further includes: storing the compary value in a storage register; and synchronizing the storing of the compare value such that the compare value is stored only after a specified number of primary and secondary datawords have been transmitted to their respective CRC circuits and a last primary and secondary CRC value has been compared.